Magnetoresistive Random Access Memory (MRAM) is a non-volatile memory technology that uses magnetic elements. MRAM is gaining popularity as the next-generation memory technology for numerous semiconductor device applications which require low cost and high speed. Several types of MRAM are well known in the art, and MRAM operation can be briefly explained using the example of a commonly used variety of MRAM, a Spin Transfer Torque MRAM (STT-MRAM). A STT-MRAM uses electrons that become spin-polarized as the electrons pass through a thin film (spin filter).
FIG. 1 illustrates a conventional STT-MRAM bit cell 100. The STT-MRAM bit cell 100 includes magnetic tunnel junction (MTJ) storage element 105 (also referred to as “MTJ stack” or simply, “MTJ”), transistor 101, bit line 102 and word line 103. MTJ 105 is formed, for example, from pinned layer 124 and free layer 120, each of which can hold a magnetic moment or polarization, separated by insulating tunneling barrier layer 122. There may be an anti-ferromagnetic (AFM) layer and a cap layer (not shown) in MTJ 105. The AFM layer is used to pin the magnetic moment of the pinned layer. The cap layer is used as a buffer layer between the MTJ and metal interconnects. The polarization of the free layer can be reversed by applying current in a specific direction such that the polarity of the pinned layer and the free layer are either substantially aligned or opposite. The resistance of the electrical path through the MTJ varies depending on the alignment of the polarizations of the pinned and free layers. This variation in resistance can be used to program and read STT-MRAM bit cell 100, as is known. STT-MRAM bit cell 100 also includes circuit elements, source line 104, sense amplifier 108, read/write circuitry 106 and bit line reference 107. Those skilled in the art will appreciate the operation and construction of STT-MRAM bit cell 100 as known in the art.
As seen from the above example, the fabrication of a conventional STT-MRAM bit cell involves integration of the various above-described components on a circuit board or semiconductor package. More specifically, memory or storage elements (e.g., MTJ 105) must be integrated with various other circuit elements (generally referred to herein, as, “logic elements”) such as, passive components, metal wires, transistors, logic gates, etc. In general, such integration requires process compatibility between the memory elements and the logic elements. Several challenges arise in this area, particularly as device technology continues to advance towards smaller and smaller device sizes.
For example, during the fabrication of MRAM devices such as STT-MRAM bit cell 100, it is important to ensure that capacitance of various components C and resistance R of various components and connections are maintained at low values. This is important for reducing cross coupling and RC delay values. Specifically, it is important to ensure low resistance contacts to MTJ 105, for example, to make connections to bit line 102 and transistor 101. It is also important to ensure that the process of making such contacts does not negatively impact capacitance of other circuit components that reside in a common dielectric layer (e.g., a common interlayer metal dielectric (IMD) layer) where MTJ 105 is formed.
Ensuring low resistance contacts, particularly to the top portion of MTJ 105, for example to couple free layer 120 to bit line 102, tends to be challenging, particularly as device technology advances and the height of MTJ 105 shrinks below 100 nm. Such extreme restrictions on MTJ sizes is seen, for example, in embedded applications where MTJ 105 would be required to fit between two adjacent metal levels, for example, one metal level layer below and one metal layer above MTJ 105, for making connections to the external components such as transistor 101 and bit line 102. Several drawbacks are seen in existing techniques for forming such contacts to MTJs. Some known approaches will be discussed below, for forming a top contact to an MTJ, where the MTJ is formed in a common IMD layer which also comprises other compatible logic elements (e.g., a vertical interconnect access, commonly known as “via”). Metal line contacts may be established in layers above and below this common IMD layer
In a first known approach for making a top contact to the MTJ, a top layer above the common IMD layer, where a top metal line can be formed, may be filled with a top IMD layer, up to an expected height of the top metal line. This height may be based, for example, according to a standard back end of line (BEOL) process (a BEOL is a well recognized part of integrated circuit fabrication, which defines specifications related to interconnections for connecting the various circuit elements, such as transistors, capacitors, resistors, etc., which may be formed on-chip). A trench etch process may then be used to create a trench in the top IMD layer to expose a top of the MTJ in the common IMD layer, following which the top metal line may be deposited in the trench to form a contact with the MTJ.
In a second known approach, a chemical mechanical polishing (CMP) or other planarization techniques may be used to expose the top of the MTJ formed in the common IMD layer. A top electrode (TE) can then be formed as a separate structure on top of the MTJ, for example, by deposition and patterning of a metal layer. A top IMD layer can be filled on top of the common IMD layer and a standard double-damascene (DD) process can be used to etch the top IMD layer with the TE as an etch stop layer to create a trench which ends on the TE on top of the MTJ.
In a third known approach, a sacrificial mandrel in the form of a non-conductive hard mask (HM) layer may be created on top of the MTJ. The sacrificial HM layer may be serve to protect the MTJ during etching, as well as, provide a means for forming an electrical connection to the MTJ. Once again, a top IMD layer may be filled to the height of the top metal line, and a trench etch can be performed to expose the sacrificial mandrel HM. The sacrificial mandrel HM may be selectively removed to form a cavity. The cavity may be filled during a standard BEOL process for forming the top metal line.
In a fourth known approach, the top IMD layer may be filled to a same level as for standard BEOL process, as in the first known approach above, for example. Following this, a small via may be patterned over the MTJ, such that the small via is contained within a lateral boundary of the MTJ (or in other words, limited to the width of the MTJ's horizontal surface area). Top contacts can be established through this small via.
Each of the above four known approaches require critical mask level or process steps for forming the MTJ contacts (e.g., the precise trench etches using the MTJ top, TE, HM, etc as etch stop layer). These critical masks and precise etch processes are expensive and add process complexity. Further, these known approaches do not scale well, and thus, are not compatible with projected physical dimension scaling for standard BEOL or MTJ for future technologies.
In yet another known approach, a layer formed of a high dielectric constant (K), such as, silicon nitride (SiN), is formed on top of the MTJ, as well as, the logic elements in the common IMD layer. This high K SiN layer is used as an etch stop layer, such that the top IMD layer is filled over this etch stop layer, and then trench etching is performed up to the etch stop layer on the MTJ side and past the etch stop layer, with a controlled etch to through the common IMD layer to form connections to layers below the common IMD layer on the logic side. However, such an approach tends to increase the parasitic capacitance (and thus, RC delay) and cross coupling on the logic side due to the presence of the high K SiN etch stop layer in the vicinity of the logic elements and the MTJ, which is undesirable.
Accordingly, there is a need in the art for avoiding the aforementioned drawbacks of known approaches for MRAM fabrication, for example, with regard to forming top contacts for MTJs.